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Up to 4 T3 ports
· Up to 112 T1 ports (28 T1 multiplexed onto a single T3)
· Up to 1024 n x DS-0 channels (where n is 1 to 24) with no T3 configured
· Up to 400 n x DS-0 channels (where n is 1 to 24) with one or more T3 configured
· Support for full-rate (clear channel) T3, Channelized T3 to T1, full-rate T1, Channelized T1, and fractional T1
· Integrated DSUs
· Internal or line-derived (loop) clocking selectable on each T3 or T1
· Loopback capabilities:
? Local and remote loopback at the T3 and T1 levels
? Response to embedded loopback commands
? Insertion of loopback commands into transmitted signal
· Bit-error-rate-testing (BERT) pattern generation and detection per channel
? Programmable pseudorandom pattern up to 32 bits long
· T3: All 0s, all 1s, 215, 220, 220 Quasi-Random Signal Sequence (QRSS), 223, alternating 0s and 1s, 1-in-8, and 3-in-24
· T1: All 0s, all 1s, 211, 215, 220, 220 QRSS, 223, alternating 0s and 1s, 1-in-8, and 3-in-24
? 32-bit error-count and bit-count registers
? Fully independent transmit and receive sections
? Detection of test patterns with bit error rates up to 10-2
· 24-hour history maintained for error statistics and failure counts, at 15-minute intervals
· 16- and 32-bit cyclic redundancy check (CRC); 16-bit default
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